1. Technical Field
The present invention generally relates to the design of very large scale integrated (VLSI) circuits and, more specifically to computer aided design (CAD) tools used in the modeling and simulation of very large scale integrated circuits.
2. Background Art
Modem electronic devices are constantly increasing in complexity and sophistication. As such, there is a constant need for improvements in the tools used to design and build modem electronic devices. Of particular importance are the tools used to model modem electronic devices.
Modem electronic devices have become so complex that it is virtually impossible to simply design and build devices with the expectation that they will function correctly the first time. As such, it is usually necessary for a design engineer to model a new circuit design to determine if it functions correctly before proceeding with the design and build process.
Hardware description languages (HDL) are a type of programming-like language used to describe electronic components in a textual rather than schematic way. Thus, HDLs allow designers to represent the functionality of a electronic device as a software program. The HDL model of an electronic device can then be simulated on a computer to see if the design will function as intended. Any problems in the design can then be corrected in the HDL model, and the correction retested with another simulation. Thus, HDLs help design engineers avoid problems that could otherwise be undetected. By modeling the hardware first, problems with the design can be detected during simulation and fixed before the hardware is actually built.
One issue with current HDL techniques is in the modeling of bidirectional wire input/outputs (I/O's). Bidirectional wire I/O is the general term for any connection that serves as both an input and an output to electronic devices. For example, bidirectional wire I/O's include the wire connection between logic circuits on VLSI chips and the packaging interconnect, the wire bond between the VLSI chips and the encapsulating package, and the leads or connection solder balls that are used to connected to packaged integrated circuit devices. The modeling of bidirectional wire I/Os is especially important for simulation of digital electronic devices. The modeling of bidirectional I/O's is complicated by the necessity of accurate timing information for signal flow in both directions. Current method of modeling bidirectional I/O's use simple switch based models to represent the bidirectional wire I/O. For example, when using the Verilog HDL language, TRAN primitives have been used as the switch to model the bidirectional wire I/O's. The TRAN primitive provides the basic functionality of the switch which is used in the model. These switch based models, while satisfying the functional requirements of modeling the bidirectional wire I/O, cannot meet the timing annotation requirements needed for accurate simulation.
Another problem in some simple HDL models is that modeling these models sometimes caused incorrect state transitions, resulting in simulation failure. For example, in some Vital HDL models, a behavioral model that used a break-before-make operation was used to model bidirectional wire I/O's. Unfortunately, the break-before-make behavior caused the model to go into a high impedance state before going into its final state. This extra transition would cause problems in some simulations. For example, when used to model a clock such a false transition to a high impedance state could cause false clock events downstream.
Thus, there currently exists no method or system that facilitates timing accurate modeling of bidirectional wire I/O's using HDL models. Therefore, what is needed is an improved method for bidirectional wire I/O modeling.